- Ph.D. in Computer Science and Engineering from Indian Institute of Technology, Indore, in 2019
- M.Tech. in Information Technology (Specialization in Banking & Information Security) from University of Hyderabad in 2015
- B.Tech. in Information Technology from West Bengal University of Technology in 2012.
- Hardware Security for Consumer Electronics (CE) Systems
- Reusable Intellectual Property Core Protection (IPP)
- High-Level Synthesis (HLS) in CAD-VLSI
- Hardware Design Optimization during HLS.
- Worked as Assistant Professor (Guest) in Indian Institute of Information Technology, Lucknow from January 2019 to December 2019
- Worked as Software Development Engineer for Test, Intern in Amazon Development Center, Bangalore from June 2015 to November 2015.
- Software Engineering & Lab
Research Grants Received
“Developing Reverse Engineering Resilient Hardware Accelerators during Architectural Synthesis” Sponsored by Science and Engineering Research Board (SERB), Department of Science and Technology, Govt. of India, 2021.
Role: Principal Investigator
Ms. Sonam Sharma, “Hardware Security” in progress since January 2023.
- Awarded, “IEEE Chester Sall Memorial Consumer Electronics Award 2020” for the Second place best paper in the IEEE Transactions on Consumer Electronics 2018
- Awarded “IEEE Consumer Electronics Society Best Paper Award 2019” in IEEE CE Society’s Flagship Conference – 37th IEEE Int’l Conference on Consumer Electronics (ICCE), LV
- Awarded “IETE Best Research Award 2018” by IETE Sub-Center, 2018
- Awarded IEEE Consumer Electronics Magazine “Best Paper Award 2018”, for the contribution on “Intellectual Property-Based Lossless Image Compression for Camera Systems”
- “IEEE Computer Society Technical Committee on VLSI – Best Paper Award” in IEEE International Symposium on Nanoelectronic and Information Systems (INIS 2017)
- Awarded “International Travel Grant” from ASP-DAC 2019, Japan for paper presentation
- Finalist in the Applied Research Competition, CSAW-2017, founded by NYU, held at IIT Kanpur
- MHRD scholarship holder in M.Tech, 2013-2015.
- Track Chair of ‘Energy Management of CE Hardware and Software Systems (EMC)’ in ICCE-Berlin 2019
- Track Chair of ‘Alternative Paradigms for Energy/Power Aware Hardware Security and IP Core Protection– Thinking beyond Encryption and Watermarking in ICCE-Berlin 2019
- Treasurer & Technical Activity Committee Member of IEEE Consumer Electronics Society Chapter – Bombay Section
- Reviewer IEEE TVLSI, IEEE TAES, IEEE Access, IET CDT
- Technical Program Committee Member of ICCE 2019.
- IEEE (Computer Society, Consumer Electronics Society, TC-VLSI)
- Dipanjan Roy “Design Process of Zero Area and Minimal Delay Overhead based IP Watermarking during Scheduling for High-level Synthesis Tools“, in IEEE VLSI Circuit and System Letters, vol. 6, no. 2, May 2020, pp. 10-12.
- Anirban Sengupta, Dipanjan Roy, Saraju P Mohanty and Peter Corcoran “Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware”, in IEEE Transactions on Consumer Electronics, vol. 64, no. 3, Aug. 2018, pp. 365-374, Impact factor ~ 1.8.
- Anirban Sengupta, Deepak Kachave and Dipanjan Roy, “Low Cost Functional Obfuscation of Reusable IP Cores used in CE Hardware through Robust Locking,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Accepted March 2018, Impact factor ~ 2.1. doi: 10.1109/TCAD.2018.2818720
- Anirban Sengupta, Dipanjan Roy, and Saraju P. Mohanty, “Triple-Phase Watermarking for Reusable IP Core Protection during Architecture Synthesis,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 4, pp. 742-755, April 2018, Impact factor ~ 2.1.
- Anirban Sengupta, Dipanjan Roy, Saraju Mohanty and Peter Corcoran, “DSP Design Protection in CE through Algorithmic Transformation Based Structural Obfuscation,” in IEEE Transactions on Consumer Electronics, vol. 63, no. 4, pp. 467-476, November 2017, Impact factor ~ 1.8.
- Anirban Sengupta, Dipanjan Roy “Impact of Hardware Steganography on DSP Core Datapath”, in Springer, CSI Transactions on ICT, Accepted, 2019.
- Dipanjan Roy, Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar, “Optimizing DSP Cores using Design Transformation”, in IEEE Consumer Electronics Magazine, vol. 7, no. 4, pp. 104- 109, May 2018, Impact factor ~ 1.4.
- Anirban Sengupta, Dipanjan Roy, Saraju Mohanty and Peter Corcoran, “A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC,” in IEEE Access, vol. 6, pp. 871-882, 2018, Impact factor ~ 3.56.
- Dipanjan Roy, and Anirban Sengupta, “Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering,” in IEEE Consumer Electronics Magazine, vol. 7, no. 3, pp. 104-109, May 2018, Impact factor ~ 1.4.
- Dipanjan Roy and Anirban Sengupta, “Multilevel Watermark for Protecting DSP Kernel in CE Systems”, in IEEE Consumer Electronics Magazine, vol. 8, no. 2, pp. 100-102, Mar. 2019, Impact factor ~ 1.4.
- Dipanjan Roy, and Anirban Sengupta, “Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis,” in Future Generation Computer Systems, vol. 71, pp. 89-101, 2017, Impact factor ~ 4.8.
- Dipanjan Roy and Anirban Sengupta, “Protecting IP core during architectural synthesis using HLT-based obfuscation,” in Electronics Letters, vol. 53, no. 13, pp. 849-851, 2017, Impact factor ~ 1.2.
- Anirban Sengupta and Dipanjan Roy, “Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach,” in IEEE Consumer Electronics Magazine, vol. 6, no. 2, pp. 118-124, April 2017, Impact factor ~ 1.4.
- Pallabi Sarkar, Dipanjan Roy, Anirban Sengupta and Mrinal Kanti Naskar, “Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices,” in IEEE Consumer Electronics Magazine, vol. 8, no. 1, pp. 92-94, Jan. 2019, Impact factor ~ 1.4.
- Anirban Sengupta, and Dipanjan Roy, “Intellectual Property-Based Lossless Image Compression for Camera Systems,” in IEEE Consumer Electronics Magazine, vol. 7, no. 1, pp. 119-124, Jan. 2018, Impact factor ~ 1.4.
- Anirban Sengupta, and Dipanjan Roy, “Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools,” in Advances in Engineering Software, vol. 110, pp. 26-33, 2017, Impact factor ~ 3.2.
- Anirban Sengupta, Dipanjan Roy, and Saumya Bhadauria, “Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs,” in Integration, the VLSI Journal, vol. 58, pp. 378-389, 2017, Impact factor ~ 0.9.